Abstract

As HPC and AI converge, the fabric must serve both latency-sensitive MPI traffic and bandwidth-hungry AI training. This talk presents the Cornelis Networks CN7000 distributed compute fabric — a 1.6 Tb/s-per-port, 72-port switch paired with a PCIe Gen7 NIC — converging Ultra Ethernet, UALink, RoCEv2, and standard Ethernet on one fabric. We cover the features that matter most to this community: hardware message matching, multi-path reliable transport, end-to-end congestion management with in-band signaling and link-level retry, and in-network collectives via programmable RISC-V vector engines at every switch port. On the software side, we walk through the libfabric provider path, verbs, and NCCL-over-OFI, and introduce EarlySim — our datamodel-driven simulation environment that lets MPI developers, including the MVAPICH community, co-design and validate against CN7000 ahead of silicon. We close with a preview of CN8000, our next-generation fabric: multiplied bandwidth with a fully distributed, scheduler-less switching architecture.

Bio

As CTO of Cornelis Networks, Charles oversees the company’s hardware and software technology stack, including architectural direction, roadmaps, and innovation. Charles has previously held senior leadership roles at IBM, Intel, Akuna Capital, and Jump Trading. At IBM, Charles managed the design and deployment of job launch and message-passing architecture for Blue Gene, Power, and x86 systems. At Intel, he advanced MPI implementations for high-performance networks and led the development and open-sourcing of libfabric. At Cornelis Networks, Charles initiated innovative software solutions for high-performance interconnects. At Akuna Capital and Jump Trading, he led teams developing ultra-low latency trading platforms. Charles holds master’s degrees in chemistry from Columbia University and computer science from the University of Minnesota.

Abstract

SRAM-based accelerators are turning low-latency inference into a practical reality. As models outgrow any single accelerator, the dominant question shifts from the chip to the system: how a model is partitioned and how the resulting pieces are connected without sacrificing the latency advantage of the underlying hardware. The interfaces and protocols built for prior generations of accelerators do not scale to the demands of modern inference—wrapping a highly capable accelerator in legacy interconnect quickly renders that interconnect the bottleneck.

This tutorial presents the communication model developed at d-Matrix to address this problem, one that remains consistent even as the underlying transport changes—whether a message crosses a chiplet, a package, a server, or a rack. It describes how streaming-mode communication across nodes over Ethernet, homogeneous or heterogeneous, underpins the disaggregation techniques shaping modern ML inference. This is enabled by two components: JetStream, a network interface for low-latency inference clusters built around Corsair, and Aviator Fabric, a control-plane software layer that makes transport transparent at scale.

To support these communication schemes, we developed a hardware-software co-designed approach to device-initiated communication that enables the lowest-latency inference path. JetStream extends interconnectivity in the inference regime into novel heterogeneous disaggregation, improving both throughput efficiency (Throughput/kW) and interactivity (TPS/user).

Bios

Sai Rahul Chalamalasetti is a Sr. Principal AI Systems Architect at d-Matrix, where he serves as the Architect for the JetStream IO Accelerator card, the SoC IO-Block Architect (Die-to-Die and Scale-Up) for the next-generation transformer accelerator, and the lead for Scale-Out connectivity for low-latency inference. Previously, he worked at Hewlett Packard Labs as a Researcher and at HPE Servers as a Hardware Engineer.

A Senior Member of IEEE, he holds 14 approved patents with 10 additional USPTO applications accepted and has authored over 30 conference and workshop publications. His research interests include datacenter systems architecture, heterogeneous architectures, interconnect fabrics, and FPGAs.

He received his Ph.D. and M.S. in Computer Engineering from the University of Massachusetts Lowell in 2012 and 2009, respectively.

David Karlov leads JetStream software development at d-Matrix, building next-generation AI inference infrastructure.  Over more than twenty years, he has combined hands-on engineering with technical leadership in the development of high-performance software systems spanning graphics, computer vision, machine learning and distributed systems, and is an inventor on numerous patents in imaging and graphics technologies.  His experience has focused on extracting performance from complex hardware and software systems, from rendering pipelines to modern AI infrastructure.

Abstract

Single-collective benchmarks give us a clean, peak snapshot of AI fabric performance, but they fail to reflect how real training workloads behave over time. In practice, AI training is inherently iterative, where each collective inherits congestion, queue state, and load-balancing decisions from previous steps. As a result, the key questions shift from peak throughput to whether the network converges, remains stable, and avoids long-tail latency under sustained load. By moving to iteration-aware and epoch-aware testing, we can expose hidden behaviors like congestion buildup, oscillation, and periodic resets at epoch boundaries.

Bios

Ankur Sheth is Senior Director for Strategic Projects at Keysight Technologies. In his current role he oversees the Network Test group’s AI initiatives including KAI DC Builder. With more than two decades of experience in the networking industry, he brings a unique perspective shaped by his expertise across engineering, product management and product marketing. His passion for networking drives him to create breakthrough products for new markets with a strong commitment to placing customer needs at the center of every decision.

Ankur holds a Masters’ in Business Administration from Indian Institute of Management, Ahmedabad and a Masters in Science degree in Electrical Engineering (Computer Networks) from University of Southern California, CA.

Eric Yu is a Solutions Architect focused on AI infrastructure validation and high-performance networking. His expertise spans AI fabrics, collective communication, RoCEv2, SONiC, congestion control, and large-scale distributed systems. He develops testing methodologies and workload emulation solutions that help organizations build reliable and scalable AI networks.

Abstract

The talk will present an HPC-AI software ecosystem of tools available on AWS, Google Cloud, Microsoft Azure, Oracle Cloud Infrastructure, and IBM Cloud based on MVAPICH MPI with support for GPUs. ParaTools Pro for E4S(TM) is a cloud image that includes agentic AI tools such as NVIDIA NemoClaw, OpenClaw, Google ADK and other AI tools such as NVIDIA NeMo(TM) and NVIDIA BioNemo(TM) optimized for GPUs and integrates with a performant remote-desktop based on Adaptive Computing’s Heidi AI/ODDC. It includes MVAPICH MPI, and supports both SLURM batch scheduler. On AWS, it supports x86, aarch64, and Trainium and Inferential nodes. E4S is a curated, Spack based software distribution of 100+ HPC, EDA, and AI/ML packages. It features AI tools such as TensorFlow, PyTorch, NVIDIA NeMo, NVIDIA BioNeMo, Ollama, vllm, Huggingface CLI, JAX, OpenAI, Google's Gemini API based chatbot, and other supporting tools including langchain, langgraph, pandas, and SciKit-Learn and supports AWS’ EFA, Google's IPUs, Infiniband on Azure, Oracle Mellanox Connect-X, IBM NVNICs with the optimized runtimes including MVAPICH MPI, NVIDIA NCCL, CUDA, NVIDIA Inference Xfer Library (NIXL), and NVSHMEM. It includes Codium, an IDE, Jupyter notebook, and visualization tools such as VisIt and ParaView all launched from a web browser without installing any additional software. This multi-user, multi-node, multi-gpu cloud image uses E4S and Spack as the core components for product integration and deployment of a range of HPC and AI/ML tools. These include performance evaluation tools such as TAU, HPCToolkit, DyninstAPI, PAPI, etc. and support both bare-metal and containerized deployment for CPU and GPU platforms. Container runtimes featured in the image include Docker, Podman, Singularity, and Charliecloud. Both Ubuntu 26.04 LTS and Rocky Linux 9.7 versions of Linux are supported. E4S is a community effort to provide open-source software packages for developing, deploying, and running scientific applications and tools on HPC platforms. It has built a comprehensive, extensible, coherent software stack that enables application developers to productively develop highly parallel applications that effectively target commercial cloud platforms.

Bio

Sameer Shende serves as a Research Professor and the Director of the Performance Research Laboratory at the University of Oregon and the President and Director of ParaTools, Inc. He serves as the technical lead of the E4S, ParaTools Pro for E4S(TM), TAU Performance System(R), and Program Database Toolkit (PDT) projects. His research interests include scientific software stacks, performance instrumentation, compiler optimizations, measurement, and analysis tools for HPC. He received his B.Tech. in Electrical Engineering from IIT Bombay in 1991, and his M.S. and Ph.D. in Computer and Information Science from the University of Oregon in 1996 and 2001 respectively.

Abstract

AI is ready to leave the lab, but the network is not ready to carry it. AI infrastructure is shifting from a compute-bound era to a connectivity-bound era. GPUs, accelerators, memory systems, and model architecture have scaled rapidly, but the network can no longer remain a passive utility. As AI workloads move into production-scale distributed deployments, interconnect bandwidth, latency, jitter, path control, observability, and long-distance throughput determine whether expensive compute capacity is fully utilized or remains stranded across hyperscalers, NeoClouds, regional data centers, and AI edge locations.

This presentation positions Scale Across as the next evolution beyond traditional data center interconnect. While conventional DCI was built for disaster recovery, storage replication, and workload migration, AI Scale Across extends backend networks for training and frontend networks for inference while preserving performance across distance. For training, the network gates utilization, collective communication, asynchronous training, and selected model-parallel approaches. For inference, distributed capacity depends on latency-aware routing, geo-distribution, KV-cache architecture, and predictable time-to-first-token performance

The proposed architecture introduces Fluid Interconnect: a programmable, xAware fabric that is traffic-aware, distance-aware, latency-aware, jitter-aware, network-aware, performance-aware, and tier-aware. This presentation introduces the 1Finity optical SmartNIC as a critical component of low-latency, high-throughput Scale Across. By placing transport acceleration at the server endpoint, the architecture combines a simplified data path, Verbs-style access, adaptable FPGA acceleration, and long-reach optical connectivity, while complementing existing intra-data-center fabrics

The objective is to convert remote, power-constrained, or stranded AI resources into usable computes through optical reach, intelligent endpoint acceleration, deterministic transport, and operational simplicity. This creates a scalable roadmap for distributed AI training, AI inference, HPC, remote GPU processing, and data-intensive platforms.

Bio

Dr. Solyman Ashrafi serves as Chief Technology Strategist at 1Finity/Fujitsu and is an accomplished executive leader with more than three decades of experience driving strategic value creation across Telecommunications, Hyperscale Cloud, and Artificial Intelligence. His career reflects a distinctive blend of technology vision, commercial execution, and enterprise-scale leadership, with a consistent focus on architecting next-generation ecosystems and translating advanced research and development into measurable business outcomes. Dr. Ashrafi advises senior executives, partners, and industry stakeholders on the economics and architecture of AI infrastructure, with particular emphasis on addressing stranded computes through the strategic alignment of interconnect, computing, sovereignty, and workload placement. His leadership spans hyperscaler, neutral colocation, and neoscalers interconnect architecture; 5G and edge network evolution; secure quantum key distribution; fluid optical interconnects; and agentic orchestration models that dynamically optimize paths, wavelengths, and bandwidth in response to policy, reliability, and energy requirements. Throughout his career, he has held multiple CTO and senior executive roles across global operators and leading technology vendors, including Nortel and Ericsson, where he converted long-range technology roadmaps into scaled commercial deployments. Previously, he played a key role in scaling metroPCS and supported its $33 billion merger with T-Mobile through product strategy, market execution, and business transformation. In addition to his operating leadership, Dr. Ashrafi has served as Managing Partner at a private equity firm, founded technology and software ventures, and contributed through advisory and board roles. He holds a PhD and advanced degrees in engineering and science and is the inventor of 140 patents and author of 85 refereed publications.

Abstract

As AI infrastructure evolves from isolated accelerator clusters to globally distributed systems, networking has become a first-order determinant of performance, efficiency, and scalability. This tutorial explores how Ethernet fabrics are emerging as the foundational interconnect technology for modern AI systems across scale-up, scale-out, and scale-across domains. The presentation will examine the differing communication patterns and performance requirements of tightly coupled GPU/XPU scale-up fabrics, large-scale distributed training and inference clusters, and region-scale AI deployments spanning multiple data centers. Topics include low-latency Ethernet switching, lossless transport mechanisms, congestion management, memory-semantic communication models, and the role of open standards such as Ultra Ethernet and emerging ESUN initiatives. Audience will gain an understanding of how advances in Ethernet switching silicon, transport protocols, and AI-aware networking architectures are enabling high-performance AI infrastructure at unprecedented scale. The tutorial will also discuss practical system architectures used in contemporary AI clusters

Bio

Niranjan Vaidya is a Distinguished Engineer and Architect in Broadcom's Core Switching Group (CSG). He leads switch and system architecture for the Tomahawk, Tomahawk Ultra and Trident families of high-performance Ethernet switches.

His focus areas span scale, performance and resiliency for compute fabrics. His contributions include high-performance programmable packet processing architectures, adaptive routing and congestion control, silicon friendly streaming algorithms, distributed synchronization at packet granularities, high-performance network telemetry, and an alphabet soup of networking protocols.

He is actively involved in the Ultra Ethernet Consortium and is the primary author of the Unified Forwarding Header (UFH) specification.

Niranjan has an MS in Computer Science from Iowa State University, and a B.Tech. with Honors in Computer Engineering from VJTI, University of Mumbai.

Abstract

The MVAPICH project has been powering HPC systems around the world for 25 years. This tutorial will provide an overview of the MVAPICH and MVAPICH-Plus libraries, the OSU MicroBenchmark (OMB) suite, and their features. We will focus on installation guidelines, runtime optimizations, and tuning parameters of these libraries with both microbenchmark and application use cases, as well as provide details on some of the latest features of MVAPICH.

Bios

Nat Shineman is a software engineer in the Department of Computer Science and Engineering at the Ohio State University. His current development work includes high performance interconnects, parallel computing, scalable startup mechanisms, and performance analysis and debugging of the MVAPICH2 library.

Benjamin Michalowicz is a PhD student at the Ohio State University under Prof. DK Panda and Prof. Hari Subramoni in the Network-Based Computing Laboratory. His research interests lie include high-performance computing (HPC), parallel/computer architectures, network-based computing for HPC, security in HPC, and parallel programming environments. Specifically, he is interested in efficiently offloading parallel programming models and computational workloads to Smart Network Cards like NVIDIA's BlueField DPUs. Ben actively contributes to the MVAPICH software and is a student member of the ACM and IEEE. Contact him at michalowicz.2@osu.edu

Abstract

Modern AI training and inference increasingly rely on high-performance communication and scalable software stacks to efficiently utilize modern HPC systems. This tutorial presents an overview of the HPC-AI software stack, a vendor-neutral, MPI-driven ecosystem that integrates leading AI frameworks, including PyTorch, TorchTitan, vLLM, and SGLang, with the MVAPICH-Plus communication runtime to enable high-performance distributed training and inference across modern CPU/GPU clusters. The tutorial covers distributed training and inference workflows, communication and runtime optimizations, and support for heterogeneous hardware and high-performance interconnects. It also discusses emerging trends in scalable AI systems and practical considerations for deploying and optimizing large AI workloads on HPC platforms.

Bios

Nawras Alnaasan is a Graduate Research Associate at the Network-Based Computing Laboratory, Columbus, OH, USA. He is currently pursuing a Ph.D. degree in computer science and engineering at The Ohio State University. His research interests lie at the intersection of deep learning and high-performance computing. He works on advanced parallelization techniques to accelerate the training of Deep Neural Networks and exploit underutilized HPC resources covering a wide range of DL applications including supervised learning, semi-supervised learning, and hyperparameter optimization. He is actively involved in several research projects including HiDL (High-performance Deep Learning) and ICICLE (Intelligent Cyberinfrastructure with Computational Learning in the Environment). Alnaasan received his B.S. degree in computer science and engineering from The Ohio State University. Contact him at alnaasan.1@osu.edu.

Jinghan Yao is a Graduate Research Associate at The Ohio State University, specializing in high-performance computing (HPC) and large-scale communication optimization for AI training and inference. His research develops efficient communication runtimes and libraries aimed at accelerating foundation model workloads. Jinghan has published papers at leading conferences including MLSys, IPDPS, and NeurIPS, and has presented his work at NVIDIA GTC 2024 and 2025. He collaborates closely with industry research teams such as Microsoft DeepSpeed to advance scalable communication techniques for AI.